1. Field of Art
The disclosure generally relates to the emulation of circuits, and more specifically to placing and routing of debugging logic in an emulated circuit.
2. Description of the Related Art
Configurable hardware design tools, such as emulators and other field programmable gate array (FPGA) prototypes have been developed to assist circuit designers in designing and debugging highly complex integrated circuits. For example, an emulator includes multiple reconfigurable components, such as FPGAs that together can imitate the operations of a design under test (DUT). By using a design tool to imitate the operations of a DUT, designers can verify whether a DUT complies with various design requirements prior to fabrication.
An aspect of imitating the operations of a DUT includes incorporating debugging logic with the DUT. Debugging logic is a circuit or a hardware component that traces signals or outputs of logic components (e.g., a register, logic gate, memory, and etc.) of the DUT. For example, debugging logic may track a number of toggles in a logic component output or track whether a logic component output has transitioned to a certain state. The information gathered by debugging logic can be used, for example, to verify the functionality of the DUT or to determine certain properties of the DUT (e.g., DUT's power consumption).
When debugging logic is placed, for example, on an FPGA that is emulating components of the DUT, outputs of DUT logic components to be traced are electrically coupled or routed to the debugging logic through a routing layer in order for the debugging logic to trace the target outputs. However, placements of debugging logic may not be optimized and contribute to inefficient routings between the logic components and the debugging logic. This can result in FPGAs that do not compile, or forcing FPGA designers to overload FPGAs with routing resources dedicated to debug or shared between the design and the debug.
Therefore, a conventional emulation environment is inefficient in terms of placing debugging logic and routing the debugging logic to logic components of a DUT.